
7
FN6808.3
October 1, 2009
LVDS OUTPUTS
Differential Output Voltage
VT
3mA Mode
620
mVP-P
Output Offset Voltage
VOS
3mA Mode
950
965
980
mV
Output Rise Time
tR
500
ps
Output Fall Time
tF
500
ps
CMOS OUTPUTS
Voltage Output High
VOH
IOH = -500A
OVDD - 0.3
OVDD - 0.1
V
Voltage Output Low
VOL
IOL = 1mA
0.1
0.3
V
Output Rise Time
tR
1.8
ns
Output Fall Time
tF
1.4
ns
Digital Specifications (Continued)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Timing Diagrams
FIGURE 1A. DDR
FIGURE 1B. SDR
FIGURE 2A. DDR
FIGURE 2B. SDR
LATENCY = L CYCLES
tDC
tPD
tA
SAMPLE N
tCPD
INP
INN
CLKN
CLKP
CLKOUTN
CLKOUTP
ODD BITS
N-L
ODD BITS
EVEN BITS
N-L + 1
N-L + 2
EVEN BITS
D[10/8/6/4/2/0]P
D[10/8/6/4/2/0]N
N
LATENCY = L CYCLES
tDC
tPD
tA
SAMPLE N
tCPD
INP
INN
CLKN
CLKP
CLKOUTN
CLKOUTP
DATA
N-L + 1
D[11/0]P
D[11/0]N
N
DATA
N-L
SAMPLE N
tDC
tPD
tA
INP
INN
CLKN
CLKOUT
CLKP
D[10/8/6/4/2/0]
LATENCY = L CYCLES
ODD BITS
N-L
ODD BITS
EVEN BITS
N-L + 1
N-L + 2
EVEN BITS
N
tCPD
SAMPLE N
INP
INN
CLKN
CLKOUT
CLKP
tCPD
tA
D[11/0]
tDC
tPD
DATA
N-L
DATA
N-L + 1
N
LATENCY = L CYCLES
KAD5512HP